1. Field of the Invention
This invention relates to computer systems and, more particularly, to methods and apparatus for providing very fast modes for writing data to a frame buffer for display on an output display device.
2. History of the Prior Art
One of the significant problems involved in increasing the speed of operation of desktop computers has been in finding ways to increase the rate at which information is transferred to an output display device. Many of the various forms of data presentation which are presently available require that copious amounts of data be transferred. For example, if a computer output display monitor is operating in a color mode in which 1024.times.780 pixels are displayed on the screen and the mode is one in which thirty-two bits are used to define each pixel, then a total of over twenty-five millions bits of information must be transferred to the screen with each frame that is displayed. Typically, sixty frames are displayed each second so that over one and one-half billion bits must be transferred each second. This requires a very substantial amount of processing power and, in general, slows the overall operation of the computer.
In order to speed the process of transferring data to the display, various accelerating circuitry has been devised. In general, this accelerating circuitry (often referred to as a graphic rendering device) is adapted to relieve the central processor of the computer of the need to accomplish many of the functions necessary to transfer data to the display. Essentially, these accelerators take over various operations which the central processor would normally be required to accomplish. For example, block transfers of data from one position on the screen to another require that each line of data on the screen being transferred be read and rewritten to a new position on a new line. Storing information within window areas of a display requires that the data available for each window portion be clipped to fit within that window portion and not overwrite other portions of the display. Many other functions require the generation of various vectors when an image within a window on the display is moved or somehow manipulated. When accomplished by a central processing unit, all of these operations require a substantial portion of the time available to the central processing unit. These repetitive sorts of functions may be accomplished by a graphics accelerator and relieve the central processor of the burden. In general, it has been found that if operations which handle a great number of pixels at once are mechanized by a graphics accelerator, then the greatest increase in display speed may be attained.
A problem which has been discovered by designers of graphics accelerator circuitry is that a great deal of the speed improvement which is accomplished by the graphics accelerator circuitry is negated by the frame buffer circuitry into which the output of the graphics accelerator is loaded for ultimate display on an output display device. Typically, a frame buffer offers a sufficient amount of dynamic random access memory (DRAM) to store one frame of data to be displayed. However, transferring the data to and from the frame buffer is very slow because of the manner in which the frame buffers are constructed. Various improvements have been made to speed access in frame buffers. For example, two-ported video random access memory (VRAM) has been substituted for dynamic random access memory (DRAM) so that information may be taken from the frame buffer at the same time that other information is being loaded into the frame buffer.
A flash write mode has been devised for allowing an entire row of a display to be written with a single color in a single access. This flash write mode is useful when the entire display is being cleared. The flash write mode is not, however, able to provide clipping to limited areas or to function with other than an entire row or rows of the display. Consequently, this mode cannot be used when information is being displayed in windows on the screen of an output display. In fact, the speedup provided by the flash write mode is only available in an operation which is used very infrequently. Thus, although a theoretically large number of pixels may be affected using this mode, the flash write operation is used so infrequently that it provides no additional operational speed for the frame buffer.
The typical frame buffer is written in a mode referred to hereinafter as normal mode. In normal mode, each pixel position of the frame buffer is separately addressed and accessed; and the pixel data is sent on the data bus to these addressed positions. For example, with a thirty-two conductor data bus, thirty-two bits defining a pixel may be placed on the bus and sent to positions in the frame buffer memory. If the computer is functioning in a thirty-two bit color mode, this data defines a single pixel; in sixteen bit color mode, two pixels; in eight bit color mode, four pixels. If a frame buffer is addressed a pixel (or two, or four) at a time, then each pixel in the frame buffer may be described by a different individual color; however, this normal mode of operation is very slow.
When text is being written into a document and to the screen by a user, individual pixels are being affected by the manipulation of the keys so the speed at which the pixel information is handled in the frame buffer is not limiting. However, there are many manipulations accomplished by graphical rendering devices in which the need to write each pixel separately to the frame buffer using the normal mode of writing makes the operation very slow. For example, when a text file is first opened in a window on the display, the writing of individual pixels makes the operation very slow. Similarly, when text is scrolled, writing individual pixels makes the operation very slow.
For this reason, a block mode of writing has been devised for frame buffers. In this block mode, the data transferred on the data bus indicates, not pixel values, but control signals signifying whether a pixel is to be written or not. A color register which is a part of the frame buffer stores a color value which is written to the pixel position if the pixel position is enabled by the control signal. Nothing is written to a pixel position which is not enabled. This block mode of operation allows simultaneous writes of the single color stored in the color register to a number of pixel positions equal to the number of conductors on the data bus. This mode may also be used to clip pixel data to a window on the display by writing a color value within the window and ignoring the pixels outside the window area.
Using this block mode of operation with a color value register speeds up writing to a frame buffer under many of the conditions in which lack of speed is most obvious. Unfortunately, this mode of operation has a number of limitations. First, it has been typically used with systems using four bit color pixels. Second, it has never been adapted for use with more that one color pixel size as might occur in modern color systems. More importantly, typical operations which are accomplished with the data in any window of the display involve a manipulation of only two colors. For example, when text is written to the screen, the color of each letter and the color of the background surrounding that letter are manipulated by varying the pixels stored in the frame buffer for describing the image on the display. Unless both colors are written, no outline is provided for the text. Both the software which provides data for display and the various graphical rendering devices which accelerate the manipulation of that data are capable of manipulating two colors at once and usually do so. However, the frame buffers which are available for desktop computers are capable of varying no more than a single color at a time in the block mode in which a number of pixels may be addressed simultaneously. Thus, though the modern rendering devices speed up the manipulation of data, the presentation slows at the frame buffer which is able to accept only a single color at a time when presented data in the block mode of operation. This problem is especially acute because each time a different color is used for a group of pixels, the color register must be updated from the old color value to the new color value in a time consuming operation before the new color may be used. Thus, a background color must be first placed in the color value register in one operation for a first row on the display. The pixels of that color must be written to the frame buffer. Then, the color must be changed in the register, and those pixels of the foreground color described in a second write operation. When, the next row of pixels is written to the frame buffer, the entire operation must be repeated again. The need to repeat the same operation for each row of the frame buffer greatly slows the speed at which pixel data may be written.
Recently, an arrangement has been devised which allows two colors to be written simultaneously in a block mode write operation. The arrangement uses a plurality of color value registers on the frame buffer to store a plurality of color values. This arrangement eliminates the necessity to reload the color value registers during the writing of a window, allows multiple color modes to be utilized, and accelerates writing dramatically. The arrangement is described in detail in copending U.S. patent application Ser. No. 08/145,756, entitled Apparatus For Providing Fast Multi-Color Storage In A Frame Buffer, Priem et al, filed on even date herewith. It is desirable to provide apparatus and methods for utilizing the arrangement described in the co-pending patent application to most effectively speed the operation of writing to a frame buffer.